A variety of semiconductor memories have recently been proposed, and among these semiconductor memories, one having a bit line below an isolation region as described in, for example, Japanese Laid-Open Patent Publication No. 05-326893 is noticeable because it can be easily highly integrated.
Now, a semiconductor memory having a bit line below an isolation region and a method for fabricating the same will be described with reference to FIGS. 59(a) through 59(d) and 60.
First, after a trapping film 2 is deposited on a silicon substrate 1 as shown in FIG. 59(a), an impurity diffusion layer 4 working as a bit line is formed through impurity ion implantation into the silicon substrate 1 with a resist pattern 3 used as a mask as shown in FIG. 59(b). Thereafter, the trapping film 2 is selectively etched by using the resist pattern 3 as a mask, so as to remove a portion of the trapping film 2 disposed above the impurity diffusion layer 4.
Next, after removing the resist pattern 3 as shown in FIG. 59(c), a LOCOS isolation region 5 is formed through thermal oxidation.
Then, after depositing a polysilicon film 6 over the semiconductor substrate 1 as shown in FIG. 59(d), the polysilicon film 6 is selectively etched, resulting in obtaining a conventional semiconductor memory as shown in FIG. 60.
The conventional semiconductor memory has, however, mainly three problems as follows:
The first problem is that refinement is difficult because the LOCOS isolation region is used for isolating devices from one another. Specifically, when the LOCOS isolation region is employed, a bird's beak is caused at the end of the isolation region, and hence, an active region becomes small as compared with a mask dimension. Therefore, it is necessary to previously set a large mask dimension, which makes refinement difficult.
The second problem is that it is difficult to lower the resistance of the bit line because the impurity diffusion layer working as the bit line is provided below the LOCOS isolation region.
The third problem is that it is difficult to lower the resistance of a gate electrode because salicide technique is difficult to employ. Specifically, as shown in FIG. 60, the impurity diffusion layer 4 working as the bit line diffuses outside the LOCOS isolation region 5. Accordingly, if the salicide technique is employed under this condition, a silicide layer is unavoidably formed in a surface portion of the impurity diffusion layer 4, so that bit lines may be short-circuited through the silicide layer. Therefore, the salicide technique is difficult to employ.